1. Field of the Invention
The present application relates to a signal transformer, and more particularly to a signal transformer capable of regulating a signal level.
2. Description of Related Art
Please refer to FIG. 1A which is a schematic circuit diagram of a conventional signal transformer for regulating a level of an input signal to a suitable level and then outputting the regulated input signal. The signal transformer includes an inverter IN, N-type transistor switches M1, M2, M5, and M6, and P-type transistor switches M3, M4, M7, and M8. The inverter IN is connected to a ground reference potential VSS and a low driving voltage reference potential VDD, and outputs an input signal TIN inversely. Sources of the N-type transistor switches M1 and M2 are connected to the ground reference potential VSS, and drains thereof are respectively connected to sources of the N-type transistor switches M5 and M6. Gates of the N-type transistor switches M5 and M6 receive a low reference potential VREFL, and drains thereof are respectively connected to sources of the P-type transistor switches M7 and M8. Gates of the P-type transistor switches M7 and M8 receive a high reference potential VREFH, and sources thereof are respectively connected to drains of the P-type transistor switches M3 and M4. Sources of the P-type transistor switches M3 and M4 are connected to a high driving voltage reference potential HVDD. A gate of the P-type transistor switch M3 is connected to the drain of the P-type transistor switch M4, and a gate of the P-type transistor switch M4 is connected to the drain of the P-type transistor switch M3.
The input signal TIN is input to a gate of the N-type transistor switch M1, and the input signal TIN is also input to a gate of the N-type transistor switch M2 after it is inverted by the inverter IN. Please refer to FIG. 1B which shows signal waveforms of the signal transformer depicted in FIG. 1A. While the input signal TIN is converted from a low level to a high level, the N-type transistor switch M1 changes from cut-off to conducting, and the N-type transistor switch M2 changes from conducting to cut-off, so that a drain potential CLSO1 of the N-type transistor switch M1 is converted from the high level to the low level (i.e. the ground reference potential VSS), and a drain potential CLSO2 of the N-type transistor switch M2 is converted from the low level to the high level. Since the transistor switches have parasitic capacitors, a delay time “Delay” exists from the beginning of converting the drain potential CLSO1 of the N-type transistor switch M1 to a steady state as well as the drain potential CLSO2 of the N-type transistor switch M2. Since a gate potential of the N-type transistor switch M6 is equal to the low reference potential VREFL, the drain potential CLSO2 of the N-type transistor switch M2 in the steady state is VREFL−Vtn, wherein Vtn (Vtn>0) is a threshold voltage of the N-type transistor switch M6. Meanwhile, while the drain potential CLSO1 of the N-type transistor switch M1 falls from the high level to the low level, a drain potential CLSO3 of the P-type transistor switch M3 also falls, so that the P-type transistor switch M4 is conducted. Accordingly, a drain potential CLSO4 of the P-type transistor switch M4 reaches to a high driving voltage reference potential HVDD, and causes the P-type transistor switch M3 to be cut-off, such that the drain potential CLSO3 of the P-type transistor switch M3 falls to and steadies in HVDD−VREFH+Vtp, wherein Vtp (Vtp>0)is a threshold voltage of the P-type transistor switch M7. Similarly, due to the parasitic capacitors of the transistor switches, the delay time “Delay” exists when the drain potential CLSO3 of the P-type transistor switch M3 and the drain potential CLSO4 of the P-type transistor switch M4 are converted to be in the steady state. While the input signal TIN is converted from the high level to the low level, the potentials CLSO2 and CLSO4 are converted from the high level to the low level after the delay time “Delay”, and the potentials CLSO1 and CLSO3 are converted from the low level to the high level after the delay time “Delay”. Through the above-described conversions, the input signal, which level is between the low driving voltage reference potential VDD and the ground reference potential VSS, is converted to two opposite signals CLSO3 and CLSO4, which levels are between the high driving voltage reference potential HVDD and (HVDD−VREFH).
Due to an obvious transient delay time is generated during the signal conversion process of the conventional signal transformer, such that the performance of the conventional signal transformer is affected. Besides, the longer is the transient delay time, the more is the switching power loss.